A PROCESSOR BASED IMPLEMENTATION OF LAPPED BIORTHOGONAL TRANSFORM FOR JPEG XR COMPRESSION ON FPGA
Abstract
This paper describes a new methodology for implementation of Lapped Biorthogonal Transform (LBT) used in JPEG XR Image compression. Due to sequential nature of LBT, we present a processor based design that executes the instructions of LBT at higher speed. This design can be used in low cost battery operated imaging devices and supports easy up-gradation. We have tested the design on Xilinx Virtex-II Pro FPGA that includes built in PowerPC 405 core which is a 32-bit implementation of RISC PowerPC embedded-environment architecture.References
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